The inventive concepts relate to semiconductor devices and methods of fabricating the same.
A three-dimensional integrated circuit (3D-IC) memory technique includes various techniques for three-dimensionally arranging memory cells to achieve an increase in memory capacity. The memory capacity may be increased by a fine pattern technique and a multi-level cell (MLC) technique as well as the 3D-IC memory technique. However, the fine pattern technique may be expensive and the MLC technique may be limited to the number of bits per cell. Thus, the 3D-IC memory technique may be an important technique for increasing memory capacity. If the fine pattern technique and the MLC technique are combined with the 3D-IC memory technique, the memory capacity may be further increased. Thus, the fine pattern technique and the MLC technique may also be developed independently of the 3D-IC technique.